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978-250-3343 tel 978-250-3373 fax Order On-line at www.hittite.com
Application Support: apps@hittite.com
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HMC700LP4 / 700LP4E
v11.0411
8 GHz 16-Bit Fractional-N PLL
Electrical Specifications, VDDCP, VCCCP = 5V; RVDD, AVDD, DVDDM, VDDPFD, DVDD,
VDDIO, DVDDQ, VCCPS, AVCC = 3.3V ±5%; AGND = DGND = 0V
Parameter
conditions
Min
typ
Max
Units
RF Input Characteristics
Max rF input Frequency (3.3V)
8
9
GHz
Min rF input Frequency
100
200
MHz
rF input Sensitivity
ac coupling only. recommended
range -10 to -5dBm. operation with
higher levels, up to +7dBm is allow-
able, but phase noise degradation
may occur.
-10
0
dBm
rF input Level Differential
ac coupling only.
-16
+6
dBm
16 bit divider (integer)
n Divide ratio, 216 + 31
32
65,567
16 bit divider (fractional)
216-1
36
65,535
REF Input Characteristics
Max ref input Frequency (3.3V)
200
MHz
Min ref input Frequency
200
kHz
ref input Sensitivity
ac coupling only. recommended
level >500mVpp. With 250mVpp
phase noise degradation may
occur.
250
3000
mVpp
ref input Level Differential
ac coupling only
250
5000
mVpp
14 bit ref Divider range
1
16,383
Phase Detector
Phase Detector Frequency (Frac)
50
70
MHz
Phase Detector Frequency (integ)
0.2
100
MHz
General Description
the HMc700LP4(E) is a SiGe BicMoS fractional-n PLL. the PLL includes a very low noise digital phase frequency
detector (PFD), and a precision controlled charge pump.
the fractional PLL features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and very
low spurious products. Spurious outputs are low enough to eliminate the need for costly Direct Digital Synthesis (DDS)
references in many applications.
the HMc700LP4(E) phase-frequency detector (PFD) features cycle slip prevention (cSP) technology that allows
faster frequency hopping times.
Ultra low in-close phase noise and low spurious also permit architectures with wider loop bandwidths for faster
frequency hopping and low micro-phonics. FSK mode allows the synthesizer to be used as a simple low cost direct
FM transmitter source.
recommended level >500mVpp. With 250mVpp phase noise degradation may occur.
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